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HA-5137/883
June 1998
60MHz, Ultra Low Noise, Precision Operational Amplifier
Description
The HA-5137/883 monolithic operational amplifier features an excellent combination of precision DC and wideband high speed characteristics. Utilizing the Intersil DI technology and advanced processing techniques, this unique design unites low noise precision instrumentation performance with high speed, wideband capability. This amplifier's impressive list of features include low VOS , wide gain-bandwidth, high open loop gain, and high CMRR. Additionally, this flexible device operates over a wide supply range while consuming only 120mW of power. Using the HA-5137/883 allows designers to minimize errors while maximizing speed and bandwidth in applications requiring gains greater than five. This device is ideally suited for low level transducer signal amplifier circuits. Other applications which can utilize the HA-5137/883's qualities include instrumentation amplifiers, pulse or RF amplifiers, audio preamplifiers, and signal conditioning circuits.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 14V/s (Min) * Wide Gain Bandwidth (AV 5) . . . . . . . . . 60MHz (Min) * Low Noise (at 1kHz) . . . . . . . . . . . . . . . 4.5nV/Hz (Max) * Low Offset Voltage. . . . . . . . . . . . . . . . . . . .100V (Max) * Low Offset Drift With Temperature. . . . 1.8V/oC (Max) * High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . 100dB (Min) * High Voltage Gain . . . . . . . . . . . . . . . . . . 700kV/V (Min)
Applications
* High Speed Signal Conditioners * Wide Bandwidth Instrumentation Amplifiers * Low Level Transducer Amplifiers * Fast, Low Level Voltage Comparators * Highest Quality Audio Preamplifiers * Pulse/RF Amplifiers
Ordering Information
PART NUMBER HA2-5137/883 HA4-5137/883 HA7-5137/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Pin Metal Can 20 Ld CLCC 8 Ld CERDIP PKG. NO. T8.C J20.A F8.3A
Pinouts
HA-5137/883 (CERDIP) TOP VIEW HA-5137/883 (CLCC) TOP VIEW
BAL BAL NC NC NC
HA-5137/883 (METAL CAN) TOP VIEW
BAL 8 18 NC BAL 1 + 3 4 V- (CASE) 5 7 V+
BAL -IN +IN V-
1 2 3 4 +
8 7 6 5
BAL V+ NC OUT NC -IN NC +IN NC 4 5 6 7 8
3
2
1 20 19
+
17 V+ 16 NC 15 OUT 14 NC +IN -IN 2
6 OUT
NC
9 10 11 12 13 NC NC NC VNC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number
1
511034-883 File Number 3714.1
HA-5137/883
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 44V Differential Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . 0.7V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 115 28 CLCC Package . . . . . . . . . . . . . . . . . . 85 26 Metal Can Package . . . . . . . . . . . . . . . 155 67 Package Power Dissipation Limit at 75oC for TJ 175oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870mW CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.18W Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645mW Package Power Dissipation Derating Factor Above 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8mW/oC Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5mW/oC Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V VINCM 1/2 (V+ - V-) RL 600
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes. 2. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 100k, VOUT = 0V, Unless Otherwise Specified. PARAMETER Input Offset Voltage SYMBOL VIO CONDITIONS VCM = 0V GROUP A SUBGROUPS 1 2, 3 Input Bias Current IB VCM = 0V, RS = 10k, 50 +I B + -I B -------------------------- 2 Input Offset Current IIO VCM = 0V, +RS = 10k, -RS = 10k V+ = +4.7V, V- = -25.3V V+ = 25.3V, V- = -4.7V VOUT = 0V and +10V, RL = 2k VOUT = 0V and -10V, RL = 2k VCM = +11V VCM = +10V -CMRR VCM = -11V VCM = -10V 1 2, 3 1 2, 3 1 2, 3 4 5, 6 4 5, 6 1 2, 3 1 2, 3 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 -75 -135 10.3 10.3 700 300 700 300 100 100 100 100 75 135 -10.3 -10.3 nA nA V V V V kV/V kV/V kV/V kV/V dB dB dB dB 1 2, 3 TEMP. (oC) 25 125, -55 25 125, -55 MIN -100 -300 MAX 100 300 80 150 UNITS V V nA nA
Common Mode Range
+CMR
-CMR
Large Signal Voltage Gain
+AVOL
-AVOL
Common Mode Rejection Ratio
+CMRR
Spec Number 2
511034-883
HA-5137/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 100k, VOUT = 0V, Unless Otherwise Specified. PARAMETER Output Voltage Swing SYMBOL +VOUT1 CONDITIONS RL = 2k GROUP A SUBGROUPS 4 5, 6 -VOUT1 RL = 2k 4 5, 6 +VOUT2 -VOUT2 Output Current +IOUT -IOUT Quiescent Power Supply Current +ICC RL = 600 RL = 600 VOUT = -10V VOUT = +10V VOUT = 0V, IOUT = 0mA 4 4 4 4 1 2, 3 -ICC VOUT = 0V, IOUT = 0mA 1 2, 3 Power Supply Rejection Ratio +PSRR VSUP = 14V, V+ = +4V, V- = -15V, V+ = +18V, V- = -15V VSUP = 14V, V+ = +15V, V- = -4V, V+ = +15V, V- = -18V Note 3 1 2, 3 1 2, 3 1 2, 3 -VIOAdj Note 3 1 2, 3 NOTE: 3. Offset adjustment range is [VIO (Measured) 1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 2k, CLOAD = 50pF, AVCL = +10V/V, Unless Otherwise Specified. PARAMETER Slew Rate SYMBOL +SR -SR Rise and Fall Time tr tf Overshoot +OS -OS CONDITIONS VOUT = -3V to +3V VOUT = +3V to -3V VOUT = 0 to +200mV 10% tr 90% VOUT = 0 to -200mV 10% tf 90% VOUT = 0 to +200mV VOUT = 0 to -200mV GROUP A SUBGROUPS 7 7 7 7 7 7 TEMP. (oC) 25 25 25 25 25 25 MIN 14 14 MAX 100 100 40 40 UNITS V/s V/s ns ns % % TEMP. (oC) 25 125, -55 25 125, -55 25 25 25 25 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 MIN 11.5 11.5 10 16.5 -4 -4 86 86 86 86 VIO-1 VIO-1 VIO+1 VIO+1 MAX -11.5 -11.5 -10 -16.5 4 4 UNITS V V V V V V mA mA mA mA mA mA dB dB dB dB mV mV mV mV
-PSRR
Offset Voltage Adjustment
+VIOAdj
Spec Number 3
511034-883
HA-5137/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Characterized at: VSUPPLY = 15V, RLOAD = 2k, CLOAD = 50pF, AV = +5V/V, Unless Otherwise Specified. PARAMETER Average Offset Voltage Drift Differential Input Resistance Low Frequency Peak-to-Peak Noise Input Noise Voltage Density SYMBOL VIOTC RIN ENP-P EN CONDITIONS VCM = 0V VCM = 0V 0.1Hz to 10Hz RS = 20, fO = 10Hz RS = 20, fO = 100Hz RS = 20, fO = 1kHz Input Noise Current Density IN RS = 2M, fO = 10Hz RS = 2M, fO = 100Hz RS = 2M, fO = 1kHz Gain Bandwidth Product GBWP VO = 100mV, fO = 10kHz VO = 100mV, fO = 1MHz Full Power Bandwidth Minimum Closed Loop Stable Gain Settling Time Output Resistance Quiescent Power Consumption NOTES: 4. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 5. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2VPEAK). 6. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on output.) TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 7. PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLES 1 AND 2) 1 1 (Note 7), 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7 1 FPBW CLSG tS ROUT PC VPEAK = 10V RL = 2k, CL = 50pF To 0.1% for a 10V Step Open Loop VOUT = 0V, IOUT = 0mA NOTES 4 4 4 4 4 4 4 4 4 4 4 4, 5 4 4 4 4, 6 TEMP. (oC) -55 to 125 25 25 25 25 25 25 25 25 25 25 25 -55 to 125 25 25 -55 to 125 MIN 0.8 60 43 220 5 MAX 1.8 0.25 10 5.6 4.5 4.0 2.3 0.6 1.5 100 120 UNITS V/oC M VP-P nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz MHz MHz kHz V/V s mW
Spec Number 4
511034-883
HA-5137/883 Die Characteristics
DIE DIMENSIONS: 104.3 x 65 x 19 mils 2650 x 1650 x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA TRANSISTOR COUNT: 63 PROCESS: Bipolar Dielectric Isolation WORST CASE CURRENT DENSITY: 3.6 x 105A/cm2 at 15mA This device meets Glassivation Integrity Test Requirement per MIL-STD-883 Method 2021 and MIL-I-38535 Paragraph 30.5.5.4. SUBSTRATE POTENTIAL (Powered Up): V-
Metallization Mask Layout
HA-5137/883
BAL BAL
-IN +IN
V+
OUT
V-
NC
Spec Number 5
511034-883
HA-5137/883 Metal Can Packages (Can)
REFERENCE PLANE A L L2 L1 A A OD OD1 Oe 2 1 Ob1 Ob BASE AND SEATING PLANE BASE METAL LEAD FINISH N k1 OD2
T8.C MIL-STD-1835 MACY1-X8 (A1)
e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Ob Ob1 Ob2 OD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94
k
OD1
C L
F Q
OD2 e e1 F k k1
0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 45o BSC 45o BSC 8 0.040 0.034 0.045 0.750 0.050 0.045 -
5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
Ob1
Ob2
L L1
SECTION A-A
L2 Q
NOTES: 1. (All leads) Ob applies between L1 and L2. Ob1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. is the basic spacing from the centerline of the tab to terminal 1 and is the basic spacing of each lead or lead position (N -1 places) from , looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH.
N
45o BSC 45o BSC 8
Spec Number 6
511034-883
HA-5137/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
aaa bbb ccc M N
Spec Number 7
511034-883
HA-5137/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B2 MIN 0.060 0.050 0.022 0.006 0.342 MAX 0.100 0.088 0.028 0.022 0.358 MILLIMETERS MIN 1.52 1.27 0.56 0.15 8.69 1.83 REF 0.56 9.09 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3
j x 45o
0.072 REF
B
E3
E
B3 D D1 D2 D3 E
0.200 BSC 0.100 BSC 0.342 0.358 0.358 -
5.08 BSC 2.54 BSC 9.09 9.09 5.08 BSC 2.54 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.91 0.08 5 5 20 1.40 1.40 2.41 0.38 9.09 1.27 BSC 8.69
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
E1 E2 E3 e e1 h j L
0.200 BSC 0.100 BSC 0.015 0.358 0.050 BSC 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015
-E-
0.007 M E F S H S B1
L1 L2 L3
L3
e
L -H-
ND NE N
-FE1 B3
E2
L2 B2
L1
e1
D1
D2
Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 8
511034-883

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